1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layer.
2. Description of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric layers on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired layer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.18 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constant <4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k dielectric material is spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), which can be deposited as a gap fill layer in a semiconductor manufacturing process. Another low k dielectric material is silicon oxycarbide that can be used as a dielectric layer in fabricating damascene features.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has good thermal conductivity and is available in a very pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch to achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e. vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, are then removed.
However, when silicon oxycarbide layers and silicon carbide layers are used as the low k material in damascene formation, less than satisfactory interlayer adhesion has been observed during processing. Some techniques for processing substrates may apply forces that can increase layering defects, such as layer delamination. For example, excess copper containing materials may be removed by mechanical abrasion between a substrate and a polishing pad in a chemical mechanical polishing process, and the force between the substrate and the polishing pad may induce stresses in the deposited low k dielectric materials to result in layer delamination. In another example, annealing of deposited materials may induce high thermal stresses that can also lead to delamination in low k dielectric materials.
Therefore, there remains a need for a process for improving interlayer adhesion between low k dielectric layers.